Electronic systems often include a number of integrated circuit devices that need to communicate with each other and/or a master processor or controller. A serial two-wire bidirectional communication system has been developed to facilitate circuit design and simplify control strategies which has been alternatively named the two wire interface (“TWI”) or inter-integrated circuit (“I2C”) bus. It is therefore to be understood that a reference to the TWI is also a reference to the I2C bus and vice versa.
The TWI includes a serial data line (“SDA”) and a clock line (“SCL”). Devices connected to the TWI can be designated as Masters or Slaves (“devices”), each of which has the capability to send or receive information.
For proper communication each device must have a unique address. This address can be hard-programmed into each device when it is manufactured, or can be assigned each time the system is “cold started” from a power-down condition. For systems with large numbers of slave devices, it is impractical to hard-program unique addresses into each device, so a method for assigning unique addresses is required. These unique addresses could be transmitted to the devices by adding additional communication lines at the cost of increasing the number of lines or “pins” of the integrated circuit (“IC”) packages, but this is considered to be an undesirable in that it increases the cost, complexity and size of the IC's.
Andersson el al. in U.S. Pat. No. 6,629,172 (“Andersson”) describes a system for assigning unique addresses to multiple devices attached to an I2C bus. As described by Andersson, when multiple devices share the I2C address the master device is unable to communicate with each device individually. Therefore, Andersson creates a circuit enable input to individually activate each device. Once a device is activated, the master device may communicate to the device a unique I2C bus address, after which the activated device only responds to the new address. Each device initially sharing the same address is activated individually until all devices have been assigned a unique address.
FIG. 1 is a block diagram illustrating a prior art system for assigning addresses to devices on a two wire interface bus. In this prior art system, each slave device is equipped with two additional pins. These additional pins are labeled “Enable In” and “Enable Out” in slave devices 108, 110, 112, and 114. The process of the prior art system begins with sending an enable signal 116 from the host processor or “Master” 102 to the first slave device 108 in the chain, followed by an address via the serial data 104 and clock 106 lines. After the address is stored in device 108, device 108 passes the enable signal to its “Enable Out” pin which is hard wired to the “Enable In” pin of the next slave device 110. The Master 102 then communicates the next address to device 110, and the process continues sequentially until all devices on the bus have their addresses.
A limitation of the prior art methods such as those described above is that each slave device must be assigned its address individually and in sequence. For a large number of slave devices, this can be very time consuming, particularly if many of the slave devices are powered up and down frequently to reduce system energy consumption.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.